So -- putting more of the firmware into CHDK hasn't helped and neither has putting less of it in. I'm fresh out of ideas. Anybody out there have a new approach?
ROM:FF810000 ; Segment type: Pure codeROM:FF810000 AREA ROM, CODE, READWRITE, ALIGN=0ROM:FF810000 ; ORG 0xFF810000ROM:FF810000 ; START OF FUNCTION CHUNK FOR sub_FF82C7E4ROM:FF810000 CODE32ROM:FF810000ROM:FF810000 loc_FF810000 ; CODE XREF: sub_FF82C7E4+E4jROM:FF810000 ; DATA XREF: ROM:off_FF823788o ...ROM:FF810000 B loc_FF81000CROM:FF810000 ; END OF FUNCTION CHUNK FOR sub_FF82C7E4ROM:FF810000 ; ---------------------------------------------------------------------------ROM:FF810004 aGaonisoy DCB "gaonisoy"ROM:FF81000C ; ---------------------------------------------------------------------------ROM:FF81000C ; START OF FUNCTION CHUNK FOR sub_FF82C7E4ROM:FF81000CROM:FF81000C loc_FF81000C ; CODE XREF: sub_FF82C7E4:loc_FF810000jROM:FF81000C LDR R1, =0xC0410000ROM:FF810010 MOV R0, #0ROM:FF810014 STR R0, [R1]ROM:FF810018 MOV R1, #0x78ROM:FF81001C MCR p15, 0, R1,c1,c0ROM:FF810020 MOV R1, #0ROM:FF810024 MCR p15, 0, R1,c7,c10, 4ROM:FF810028 MCR p15, 0, R1,c7,c5ROM:FF81002C MCR p15, 0, R1,c7,c6ROM:FF810030 MOV R0, #0x3DROM:FF810034 MCR p15, 0, R0,c6,c0ROM:FF810038 MOV R0, #0xC000002FROM:FF81003C MCR p15, 0, R0,c6,c1ROM:FF810040 MOV R0, #0x33ROM:FF810044 MCR p15, 0, R0,c6,c2ROM:FF810048 LDR R0, =0x10000033ROM:FF81004C MCR p15, 0, R0,c6,c3ROM:FF810050 MOV R0, #0x40000017ROM:FF810054 MCR p15, 0, R0,c6,c4ROM:FF810058 LDR R0, =0xFF80002DROM:FF81005C MCR p15, 0, R0,c6,c5ROM:FF810060 MOV R0, #0x34ROM:FF810064 MCR p15, 0, R0,c2,c0ROM:FF810068 MOV R0, #0x34ROM:FF81006C MCR p15, 0, R0,c2,c0, 1ROM:FF810070 MOV R0, #0x34ROM:FF810074 MCR p15, 0, R0,c3,c0ROM:FF810078 LDR R0, =0x3333330ROM:FF81007C MCR p15, 0, R0,c5,c0, 2ROM:FF810080 LDR R0, =0x3333330ROM:FF810084 MCR p15, 0, R0,c5,c0, 3ROM:FF810088 MRC p15, 0, R0,c1,c0ROM:FF81008C ORR R0, R0, #0x1000ROM:FF810090 ORR R0, R0, #4ROM:FF810094 ORR R0, R0, #1ROM:FF810098 MCR p15, 0, R0,c1,c0ROM:FF81009C MOV R1, #0x40000006ROM:FF8100A0 MCR p15, 0, R1,c9,c1ROM:FF8100A4 MOV R1, #6ROM:FF8100A8 MCR p15, 0, R1,c9,c1, 1ROM:FF8100AC MRC p15, 0, R1,c1,c0ROM:FF8100B0 ORR R1, R1, #0x50000ROM:FF8100B4 MCR p15, 0, R1,c1,c0ROM:FF8100B8 LDR R2, =0xC0200000ROM:FF8100BC MOV R1, #1ROM:FF8100C0 STR R1, [R2,#0x10C]ROM:FF8100C4 MOV R1, #0xFFROM:FF8100C8 STR R1, [R2,#0xC]ROM:FF8100CC STR R1, [R2,#0x1C]ROM:FF8100D0 STR R1, [R2,#0x2C]ROM:FF8100D4 STR R1, [R2,#0x3C]ROM:FF8100D8 STR R1, [R2,#0x4C]ROM:FF8100DC STR R1, [R2,#0x5C]ROM:FF8100E0 STR R1, [R2,#0x6C]ROM:FF8100E4 STR R1, [R2,#0x7C]ROM:FF8100E8 STR R1, [R2,#0x8C]ROM:FF8100EC STR R1, [R2,#0x9C]ROM:FF8100F0 STR R1, [R2,#0xAC]ROM:FF8100F4 STR R1, [R2,#0xBC]ROM:FF8100F8 STR R1, [R2,#0xCC]ROM:FF8100FC STR R1, [R2,#0xDC]ROM:FF810100 STR R1, [R2,#0xEC]ROM:FF810104 STR R1, [R2,#0xFC]ROM:FF810108 LDR R1, =0xC0400008ROM:FF81010C LDR R2, =0x430005ROM:FF810110 STR R2, [R1]ROM:FF810114 MOV R1, #1ROM:FF810118 LDR R2, =0xC0243100ROM:FF81011C STR R2, [R1]ROM:FF810120 LDR R2, =0xC0242010ROM:FF810124 LDR R1, [R2]ROM:FF810128 ORR R1, R1, #1ROM:FF81012C STR R1, [R2]ROM:FF810130 LDR R0, =unk_FFB2E3F4ROM:FF810134 LDR R1, =0x1900ROM:FF810138 LDR R3, =0x140E4ROM:FF81013CROM:FF81013C loc_FF81013C ; CODE XREF: sub_FF82C7E4-1C69CjROM:FF81013C CMP R1, R3ROM:FF810140 LDRCC R2, [R0],#4ROM:FF810144 STRCC R2, [R1],#4ROM:FF810148 BCC loc_FF81013CROM:FF81014C LDR R1, =0xB0B68ROM:FF810150 MOV R2, #0ROM:FF810154ROM:FF810154 loc_FF810154 ; CODE XREF: sub_FF82C7E4-1C688jROM:FF810154 CMP R3, R1ROM:FF810158 STRCC R2, [R3],#4ROM:FF81015C BCC loc_FF810154ROM:FF810160 B loc_FF8101A4ROM:FF810160 ; END OF FUNCTION CHUNK FOR sub_FF82C7E4
I searching in the forum how to implent. Should it be added to boot.c? how?
jeff666, what do think bout using the s5is code as a template for the g9(as v3rtex suggested)?
I was looking to the s5is boot.c, it implements a complete sub_ff810000, but from my ida's dump ff810000, looks like this:
thank you for the advice and the WriteSDCard information. I can see that it will be most helpful. I notice that there are some dump functions toward the end of platform/s5is/sub/101a/boot.c. Would these be useful after a partial CHDK boot?
I'm still processing the "8 - 12 hours for an experienced developer to port CHDK" estimate from an earlier post.
void __attribute__((naked,noinline)) sub_FF81517C_my() { //"taskcreate_ClockSave\n"typedef int (*f_w)(int, int, int, int); int main() { f_w WriteSDCard; WriteSDCard=(f_w)(0xFF928CF4); // address from A720 WriteSDCard(0, 1024, 2048, 0x1900);} asm volatile ( //ok "MOV R0, #1\n" "MOV R1, #0x40000000\n" "STMFD SP!, {R3,LR}\n" "STR R0, [R1,#0x7C4]\n" "RSB R1, R1, R0,LSL#22\n" "STR R0, [R1,#0x30]\n" //ok "BL sub_FF81B7F4\n" // j_IRQdisable "MOV R2, R0\n" "BL sub_FF815144\n" "MOV R0, R2\n" "BL sub_FF81B7F8\n" //j_IRQrestore "MOV R3, #0\n" "STR R3, [SP,#8-8]\n" //[SP,#8+var_8]:"var_8 = -8\n" //ok "LDR R3, =0xFF8150CC\n" // task_ClockSave, was adr "MOV R2, #0x200\n" "MOV R1, #0x20\n" //ok "LDR R0, =0xFF8152B4\n" // aClocksave, was adr //ok "BL sub_FF81BAF0\n" // CreateTask //ok "LDMFD SP!, {R12,PC}\n" );}; //#fe
I think I've found the address of function WriteSDCard, it should be FF928CF4 (g9/100f).
it didn't generate any new file on the sd card. What's wrong?
can you help me to implement the writesdcard?