For normal usbremote sync my understanding is that if, at switch release, the current count is less than a fixed "critical valueâ€ then the shot will occur immediately & that if the current count is equal to or greater than this critical value then the shot will occur at the end of the following period.

vnd's attempt to address the challenge is stated in the precision sync code here:

https://chdk.setepontos.com/d/8312/104

i.e.

For any current count less than 10 from end of period in which switch release occurs:
if at switch release the current count is less than 10 from the end of the period count an attempt to write an extended period count to the count register (GPIO_VSYNC_MAX) is only initiated after the period count has reset to zero i.e. this attempt begins at the beginning of the subsequent normal period count and if successful will be written to GPIO_VSYNC_MAX at the end of that normal period count. The extended count in these circumstances is calculated as:

2xstd period count less (maximum period count less count at switch release)
(i.e. equivalent to 1xstandard period + counts to end of current period)

After 40ms from the beginning of this extended count its current count is examined by Canon. Assuming a non-extended count is less than 40ms then this current count will always be greater than the â€œcritical valueâ€ and the shot will occur at the end of the unextended count following the extended count.

For any current count equal or greater than 10 from end of period in which switch release occurs:
if at switch release the current count is 10 or more from the end of the period count an attempt to write an extended period count to GPIO_VSYNC_MAX begins immediately and, if successful, will be written to the register at the end of this normal period count. In this case, the extended count is calculated as:

3xstd period count less (maximum period count less count at switch release)
(i.e. equivalent to 2xstandard period + counts to end of current period)

Again, after 40ms from the beginning of this extended count its current count is examined by Canon. Assuming a non-extended count is less than 40ms then this current count will always be greater than the â€œcritical valueâ€ and the shot will occur at the end of the unextended count following the extended count.

In summary, assuming the extended count values are applied to GPIO_VSYNC_MAX in the fashion described then precision sync will occur at practically the same time in both circumstances described at the end of the normal count period which follows the two differently calculated extended periods â€" this causes all the shots to occur at 4x std periods from switch release (practically always with less than 1ms variance).

My understanding of why vnd only attempts to apply the extended count after the end of the count in which switch release occurs (only when the current count is within a count of 9 from its end) is due to the amount of processing involved with changing the image sensor from free-running to image capture mode i.e. if we are close to the end of the period there is a good chance an attempt to apply the extended count to to GPIO_VSYNC_MAX will not be successful so just wait until next std period before trying to do so.

If that was vndâ€™s supposition then it seems nearly as likely that, at switch release, a count of 10 (rather than 9 for example) from the end of the count would fail in any attempt to have an extended count written to GPIO_VSYNC_MAX by the end of the period in which the switch release occurred.

So, if occasionally this 10 count (or other close to it but not less than 10) does fail to update GPIO_VSYNC_MAX before the end of the switch release std period then it seems likely that the extended count will, instead, be written to GPIO_VSYNC_MAX at the end of the following unextended period but at a value of:
3xstd count less (maximum period count less count at switch release)

This event would lead to the precision sync outlier occurring a full std period after all other precision sync shots i.e. from switch release the shot would occur at the end of the std period following the extended period â€" the shot occurs 5xstd periods after switch release.

However, we do not see this by experiment. Instead the precision sync outlier seems to occur a single std period prior all other precision sync shots as the diagram here displays â€" the shot occurs 3xstd periods after switch release.:
https://chdk.setepontos.com/d/8312/106

My understanding of what lies beneath the precision sync outlier must therefore be wrong but I canâ€™t currently see where.

If anyone could usefully comment as to what could conceivably be behind theoutlier timing occurrence it could relieve a headache.

[hr]
fmi, related threads:
https://chdk.setepontos.com/d/11256/1
https://chdk.setepontos.com/d/11376/1