reyalp
That said, CHDK does a lot of things that are bad and scary in a multi-core environment, for example, all the things that wait in a loop on a variable set in another task.
This was a silly comment on my part 😳 That kind of thing would only be a problem if there was no coherency between the cores, but the Canon firmware likely wouldn't work that way either.
FWIW, I did some digging in the documentation.
CHDK cpuinfo (from phil's g7x2) says
Mem model feature 0 0x00100103
VMSA support 0x3 3
PMSA support 0x0 0
Cache coherence 0x1 1
...
"ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition" (ARM DDI 0406C.c) section "B4.1.89 ID_MMFR0, Memory Model Feature Register 0, VMSA" calls bits 8-11 (labeled above as "Cache coherence") "Outermost shareability" with 0b0001 meaning "Implemented with hardware coherency support."
What does "hardware coherency support" mean?
"ARM® Cortex❄¢-A Series Version: 4.0 Programmer’s Guide" (ARM DEN0013D) section "18.5 Cache coherency"
Suggests should be pretty much automatic as long as the SMP bit is set (which it is) and the MMU tables have the appropriate shareability settings.
Whether things like modules where we do explicit cache maintenance are OK is less clear. If the L2 cache is shared between cores, and unified, it seems like it might be.
