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Getting CPU configuration from CP15

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Offline reyalp

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Getting CPU configuration from CP15
« on: 14 / August / 2008, 07:33:57 »
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Here is a preliminary patch (against juciphox 481) to interrogate the System Control Coprocessor, also know as CP15.

Also attached is the resulting CPUINFO.TXT from my a540

See http://infocenter.arm.com/help/topic/com.arm.doc.ddi0155a/DDI0155.pdf for the meanings of the various fields. It's quite possible (even likely!) that I've messed up in the decoding of one or more fields. When in doubt, consult the hex values.

I'd be interested to see what you get on a Digic-III camera.
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Offline fudgey

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Re: Getting CPU configuration from CP15
« Reply #1 on: 14 / August / 2008, 08:20:20 »
Hm I tried patch -p0 < cpuinfo-pre-1.patch  on juciphox 482 (which compared to 481 is the same for the files the patch changes) but it failed at core/gui.c and include/platform.h...
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Offline whim

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Re: Getting CPU configuration from CP15
« Reply #2 on: 14 / August / 2008, 10:03:11 »
After applying the patch against juciphox482 manually, the compiler (standard Windows devkit) gives me:
(Murphy says this is more likely to happen if you're dying to try it out  :D)

Quote
cpuinfo.o: In function `cpuinfo_write_file':
cpuinfo.c:(.text+0xe4): undefined reference to `debug_read_cpuinfo'
collect2: ld returned 1 exit status
E:\CHDK\gcc\bin\gmake[1]: *** [main.elf] Error 1
gmake: *** [all-recursive] Error 1

wim

debug_read_cpuinfo(...) is declared 'void' in platform.h, which is included in both lib.c and cpuinfo.c,
and debug_read_cpuinfo(...) is defined in lib.c ...
shouldn't cpuinfo.c 'see' an 'external void' declaration ?


« Last Edit: 14 / August / 2008, 10:22:16 by whim »
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Offline reyalp

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Re: Getting CPU configuration from CP15
« Reply #3 on: 14 / August / 2008, 13:55:28 »
You probably have to build clean, since lib.c is actually included and the makefiles don't have include deps. The patch is from tortoise which may have confused gnu patch ?

edit: beware of line endings too, the tree seems to be randomly mixed dos and unix and no eol-style:native set in svn.
« Last Edit: 14 / August / 2008, 14:08:47 by reyalp »
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Offline chr

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Re: Getting CPU configuration from CP15
« Reply #4 on: 14 / August / 2008, 14:21:36 »
Hi reyalp!

This information is very helpful! I'm now compiling chdk with -mcpu=arm946e-s and now gcc eats "strd" ;)

Well, lets see what happens if I run this in qemu *g*
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Offline fudgey

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Re: Getting CPU configuration from CP15
« Reply #5 on: 14 / August / 2008, 14:58:06 »
Quote from: reyalp on 14 / August / 2008, 13:55:28
edit: beware of line endings too, the tree seems to be randomly mixed dos and unix and no eol-style:native set in svn.

Hm yes well it does complain about those for all the files, just fails those two.
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Offline reyalp

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Re: Getting CPU configuration from CP15
« Reply #6 on: 14 / August / 2008, 16:00:52 »
Turns out some platforms don't include generic/lib.c

If you put the debug_read_cpuinfo in some other file (probably needs to be arm, not thumb) it should be fine.
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Offline PhyrePhoX

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Re: Getting CPU configuration from CP15
« Reply #7 on: 14 / August / 2008, 16:18:13 »
s3is text attached.
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Offline reyalp

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Re: Getting CPU configuration from CP15
« Reply #8 on: 14 / August / 2008, 16:24:45 »
All the cameras check so far (s3is, sx100is and a540) appear to be identical CPUs, the only difference being slightly different memory protection configuration because of differing ROM addresses.
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Offline reyalp

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Re: Getting CPU configuration from CP15
« Reply #9 on: 14 / August / 2008, 21:56:33 »
Brief summary for those aren't sure what all the stuff in CPU info means:
All cameras reported so far use an ARM946ES rev 1 CPU, with 8k of instruction and data cache (4 way associative, 8 words/line), 4k instruction and data of "tightly coupled memory"

This is an ARM architecture 5TE chip.
Note: ARM model numbers, like ARM946ES should not be confused with ARM architecture versions, like ARMv5TE.

The TE suffix means that ARM DSP Instruction Set Extensions are available.

The implementor (=ARM) and variant (=0) fields suggest this is a plain jane implementation, at least as far as arm code is concerned.

A memory protection (MPU) unit is present, a memory management unit (MMU) is not.

Clock speed is unknown, but strings in my ROM suggest variable between 18mhz and 72mhz (but there are three different ones, H, L and M, and they might refer to base values to which multipliers are applied. The arm docs mention HCLK and CLK) The addresses which get/set these seem pretty obvious, so I may have more on that later.

Intentionally self-replying in case someone wants to move the svn stuff to a different thread ;)
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