Edit (30 Nov 2018):
all comments below the double horizontal rule here were made before realising that vnd's precision sync code was added to chdk trunk in 2014.
The entire comment is probably misleading so probably best to ignore but will leave in place for the record only.
To clarify
Ok.
There have always been outliers.
My current understanding/theory is that the vast majority of these outliers have been associated with current counts greater than the "critical value" at switch release and that the smaller the fraction of a standard count this critical value is then the longer the potential time between the larger than critical value count and the end of the subsequent standard period (i.e. worse sync results).
For S95, reading the testing sync thread, the std period is 272 & critical value is 224. On switch release, immediate sync within 1 or 2ms should, nearly always occur in 82% of cases. Assuming a std period of 32ms the 18% of outliers should, mostly, vary between around
(((272-225) / 272) + 1) x 32ms = 37.53ms & 32ms
in absolute terms from switch release.
If the A1200 critical value was a much smaller fraction of the std period it could help explain (or not) why no shot occurred immediately on switch release and the sync variances were all between 40 & 63ms - the critical count would need to be very low to account for the 63ms timing though which dampens the theory.
At critical count 541 and std period 620, SX150IS sync (i.e. nearly always within 2ms of immediate switch release) is 87% and inherently better than S95.
I am not aware of any absolute sync measurement times other than your own diagram.
