I can confirm that the firmware does seem to start at FC020000, and I've modified the dumper script to account for that.
In IDA (v6.4), I set the processor architecture to ARM (not ARMB), and the specific type to ARMv7-A&R. Since IDA apparently enables THUMB instructions using a fake register T, I set that register (alt-G) to 1, pressed C at address FC020000, and got valid code that begins with a jump over the signature:
ROM:FC020000 CODE16
ROM:FC020000 B.W loc_FC02000C
ROM:FC020000 ; ---------------------------------------------------------------------------
ROM:FC020004 DCB 0x67 ; g
ROM:FC020005 DCB 0x61 ; a
ROM:FC020006 DCB 0x6F ; o
ROM:FC020007 DCB 0x6E ; n
ROM:FC020008 DCB 0x69 ; i
ROM:FC020009 DCB 0x73 ; s
ROM:FC02000A DCB 0x6F ; o
ROM:FC02000B DCB 0x79 ; y
ROM:FC02000C ; ---------------------------------------------------------------------------
ROM:FC02000C
ROM:FC02000C loc_FC02000C ; CODE XREF: ROM:FC020000j
ROM:FC02000C LDR.W SP, =0x80010000
ROM:FC020010 BL sub_FC020064
ROM:FC020014 LDR R2, =0xC0242010
ROM:FC020016 LDR R1, [R2]
ROM:FC020018 ORR.W R1, R1, #1
ROM:FC02001C STR R1, [R2]
ROM:FC02001E LDR R0, =0xFC9538D4
ROM:FC020020 LDR R1, =0x10C1000
ROM:FC020022 LDR R3, =0x10E03C4
ROM:FC020024
ROM:FC020024 loc_FC020024 ; CODE XREF: ROM:FC020030j
ROM:FC020024 CMP R1, R3
ROM:FC020026 ITT CC
ROM:FC020028 LDRCC.W R2, [R0],#4
ROM:FC02002C STRCC.W R2, [R1],#4
ROM:FC020030 BCC loc_FC020024
ROM:FC020032 LDR R0, =0x10C1000
ROM:FC020034 LDR R1, =0x1F3C4
ROM:FC020036 BL sub_FC12DD3A
ROM:FC02003A LDR R0, =0xFC932474
ROM:FC02003C LDR R1, =0x8000
ROM:FC02003E LDR R3, =0x29460
and so on. Next step, see if I can find any asserts.